1. Field of the Invention
The present invention relates to a semiconductor memory device having a test circuit suitable for a burn-in test for a static memory device and the like.
2. Description of the Related Art
Generally all semiconductor memory devices undergo a lifetime accelerated test called a burn-in test before they are shipped. The test aims at screening the initial, latent defects by applying a stress to all circuits of chips for a given period of time under the circumstances of the maximum values of high temperature and high-voltage power supply allowed within the specifications or the values thereof beyond them.
The amount of stress applied to memory cells during the burn-in test causes a problem as the memory cells increase in capacity. The burn-in test for the memory cells is carried out by applying a high field stress to a transistor of each of the cells to be selected. If, in the burn-in test, the stress is uniformly applied to all the memory cells within a given period of time, the time required for applying the stress to each cell decreases as the memory cells increase in number. If the amount of stress reduces, the lifetime accelerated test for defects cannot be performed completely, with the result that the primary objective of the burn-in test cannot be attained. To sufficiently obtain the effect of the burn-in test, the time required for the burn-in test has to be increased in proportion to the memory capacity.
The burn-in test is hindered by not only the memory capacity but also the other factors. One of them is an automatic power-down function incorporated into a semi-conductor memory device. The objective of the function is to decrease the power consumption of a large-capacity memory when it is normally operated.
FIG. 12 schematically shows an asynchronous static memory incorporating an automatic power-down function. In this memory, when the logical level of a row address input changes, the selective states of an address buffer (ADB) 11, a row predecoder (RPDC) 12, and a row decoder (RDC) 13 change, and a word line corresponding to a new row address of a memory cell array (MCA) 14. Similarly, when the logical level of a column address input changes, an address buffer (ADB) 15, a column predecoder (CPDC) 16, and a column decoder (CDC) 17 operate, and a column switch corresponding to a new column address turns on. Data of memory cells selected by the row address and column address is transmitted to a sense amplifier (SA) 18 through a data line and then amplified. The amplified data is output from a data output terminal 21 through a data latch circuit (DL) 19 and a data output circuit (DO) 20 as new address data.
FIG. 13 schematically shows the ADB 11, RPDC 12, and RDC 13. In FIG. 13, the same elements as those of FIG. 12 are denoted by the same reference numerals. The circuit shown in FIG. 13 includes equivalents for the ADB 15, CPDC 16, and CDC 17 shown in FIG. 12.
In the circuit shown in FIG. 12, address transition detectors (ATD) 22 and 23 detect the transition of an address to generate a pulse signal .phi.ATD, and an internal sync pulse generation circuit (ISPG) 24 operates to generate various types of internal pulse signals. For example, an internal pulse signal .phi.DC is a signal for canceling the preceding address data remaining on the data line, and an internal pulse signal .phi.TR is a signal for resetting a delay timer circuit (DTC) 25. The DTC 25 is reset in response to the signal .phi.TR and then stops transmitting an automatic power-down signal .phi.PD for a fixed period of time. More specifically, the DTC 25 receives the internal pulse signal .phi.TR from the ISPG 24 in accordance with the transition of an address and stops transmitting the automatic power-down signal .phi.PD for a preset period of time, that is, for a period of time necessary for outputting new address data. After the time passes, the DTC 25 returns and controls the RDC 13 and SA 18 to release the selection of a memory cell and stop the SA 18. The operation of the DTC 25 shortens the time for selecting a memory cell in the normal operation mode and decreases the power consumed by the memory cells and sense amplifier.
However, the power-down function causes a great problem in the burn-in test. Since the time for maintaining the selective state after a memory cell is selected is shortened by the automatic power-down function, the stress applied to the memory cell is greatly reduced, with the result that a memory having the automatic power-down function requires a very long time to sufficiently obtain the effect of the burn-in test.
To resolve the above drawback, a memory device having a function of rendering all memory cells in a selective state at the same time is developed. In this memory device, a logic circuit is added to a row decoder to render all outputs of the decoder in the selective state, and another logic circuit is added to an automatic power-down circuit to inhibit the automatic power-down function from being carried out.
FIG. 14 is a circuit diagram showing the circuit of FIG. 13 into which a function of simultaneously selecting all memory cells. The function will now be described, comparing FIGS. 13 and 14. In FIG. 14, A1 to A4 indicate address input terminals, .phi.PD denotes an automatic power-down signal, and .phi.ND shows a word line inhibit signal for inhibiting a word line connected to a normal memory cell from being selected when a redundant memory cell is selected. The signal .phi.PD is normally at a low level, and maintains a high level for a given period of time after the transition of an address. The level of the signal .phi.ND is kept at low when no redundant memory is used. The circuit of FIG. 14 differs from that of FIG. 13 in that the row predecoder 12 and row decoder 13 are controlled by a test enable signal /.phi.TE (/indicates an inverted signal). The test enable signal /.phi.TE is supplied to the row predecoder 12, and then to a NAND circuit 26, together with the automatic power-down signal .phi.PD. The output signal of the NAND circuit 26 is supplied to the row decoder 13. The test enable signal /.phi.TE is set at a high level in the normal operation mode and a low level in the burn-in test mode, and supplied from an external input terminal (not shown) or a detection circuit for detecting the burn-in test mode.
In the normal operation mode, in other words, when the level of the test enable signal /.phi.TE is high, the operations of the circuits shown in FIGS. 13 and 14 are the same. In the circuit of FIG. 14, if the test enable signal /.phi.TE is set to a low level in the burn-in test mode, the output signals of the row predecoder 12 are all set to a high level, in other words, all addresses are rendered in a selective state irrespective of the address input state.
The output signal of the NAND circuit 26 for receiving the test enable signal /.phi.TE and automatic power-down signal .phi.PD at the same time, is fixed to a high level, and the word lines are to be selected by the row decoder 13, irrespective of the state of the automatic power power-down signal .phi.PD. If, as described above, the logic of the predecoder and row decoder is changed, the word lines of all the memory cells can be set in the selective state.
The above description of the row address is very true of the column address.
The above description the memory device is logically clear, and the device is excellent in that all the memory cells can be set in the selective state by simply modifying a logic circuit. Since, however, an additional logic circuit is included in a memory cell selecting system in the normal operation mode, it has an adverse influence on the operation speed of a memory device aiming at a high-speed operation.
In general, a large-capacity memory device includes redundant memory cells for compensating for defective ones. In this memory device, an electric stress has to be applied to the redundant memory cells in the burn-in test.
FIG. 15 shows an example of a control circuit for the redundant memory cells. A generally-used redundant memory cell control circuit includes a plurality of program circuits 41 for recording defective addresses, a plurality of comparison circuits 42 for comparing an input address and a programmed address, a plurality of selection circuits 43 for selecting redundant word lines RWL1, RWL2, . . . connected to the redundant memory cells in response to the signals output from the comparison circuits 42, and a generation circuit 44 for generating the above-described word line inhibit signal .phi.ND. In order to forcibly select all the memory cells in the burn-in test mode in the control circuit, the selection circuits 43 and generation circuit 44 have to be controlled by the test enable signal .phi.TE, as in the circuit shown in FIG. 16. Therefore, in the normal operation mode, a large timing margin is needed in the transition from an address of a defective memory cell to that of a normal one, with the result that great restrictions are imposed on the circuit in order to secure an operation margin.